1. Technical Field
The present invention relates to a photoelectric conversion device having a solid-state imaging device and a light receiving elements such as a photocoupler and a method of manufacturing the same, and, in particular, the present invention relates to techniques suitable for use in an active XY addressing type solid-state imaging devices among solid-state imaging devices (so-called CMOS sensors) compatible with the CMOS manufacturing process.
2. Background Art
Conventional solid state iamging device of a transfer layer method which transfer photoelectrically converted signal charges, are classified into MOS-type and CCD-type. These solid state imaging devices, in particular CCD-type solid state imaging devices, have been recently used for camera and VTR units, digital cameras, facsimile systems, etc., and technical development is now under way for improving the characteristics.
The CCD sensor is a type that has a photoelectric conversion portion in which photoelectric transducers corresponding to pixels are arranged in a two-dimensional array, and sequentially reads signals of each pixel which have been converted into electric charges by the photeoelectric conversion portion, with a vertical transfer CCD and a horizontal transfer CCD.
The CMOS sensor does not use a CCD for vertical and horizontal transfer, and reads pixels selected by a selection line constituted by aluminum lines or the like, as with a memory device.
Here, the CCD sensor requires a plurality of positive and negative power supply potentials, while the CMOS sensor can be driven by a single power supply, enabling lower power consumption and lower voltage compared to the CCD sensor.
Moreover, since the CCD sensor uses a special process, it is difficult to directly apply the CMOS circuit manufacturing process thereto. On the other hand, the CMOS sensor uses the CMOS circuit manufacturing process. Hence it is possible to form a logic circuit, an analog circuit, an analog to digital conversion circuit or the like at the same time, by means of a CMOS process widely used in processors, semiconductor memories such as DRAMs, logic circuits, etc. That is, the CMOS sensor can be formed on a semiconductor chip the same as that for semiconductor memories and processors, and can share the production line with semiconductor memories and processors. One example of an image sensor which is such a CMOS sensor is shown in FIG. 13.
In FIG. 13, reference numeral 100 denotes an image sensor (CMOS sensor). This CMOS sensor 100 is provided with a timing generation portion 102, an image sensor portion 101, a vertical scanning portion 103 and a horizontal scanning portion 104 for selecting an output of a pixel, an analog signal processing portion 105, an A/D portion (A/D conversion portion) 109 for performing analog to digital conversion, a digital signal processing portion 107 for converting the digitalized signal into an output signal, and an interface portion (IF portion) 108 for outputting digital image data to the outside and receiving command data from the outside.
The image sensor portion 101 is an aggregate of basic cells of the CMOS sensor, as described later. The vertical scanning portion 103 is for controlling the vertical scanning of the basic cells in the image sensor portion 101, and the horizontal scanning portion 104 is for controlling the horizontal scanning of the basic cells in the image sensor portion 101. These portions perform respective scanning control with a timing signal output from the timing generation portion 101.
The analog signal processing portion 105 subjects the image signal read from the image sensor portion 101 to required processing and outputs the signal to the A/D conversion portion 109. The A/D conversion portion 109 then converts the image signal into a digital signal and outputs the signal to the digital signal processing portion 107, which in turn outputs the image signal to the interface portion 108.
The interface portion 108 can output to the outside the digital image data output via the digital signal processing portion 107, and can also input commands from the outside. As a result, the respective constituents are controlled so as to perform control corresponding to the received commands to enable control of the mode and the output signal form of the image sensor 100 and the signal output timing, corresponding to the commands.
Here, the A/D conversion portion 109, the digital signal processing portion 107, and the interface portion 108 constitute a logic circuit portion 106. Moreover, the digital signal processing portion 107 includes a memory portion. The memory portion may be constructed such that this stores image data for one or a plurality of lines, one or a plurality of blocks and one or a plurality of frames, required for the signal processing, with these being utilized for the signal processing in the digital signal processing portion 107.
Next, a conventional basic cell in the image sensor portion 101 of the CMOS sensor 100 is shown in FIG. 14A. In FIG. 14, reference numeral 10 denotes a basic cell (CMOS sensor), 11 denotes a p-type semiconductor substrate, 12 denotes a p-type well layer formed on the p-type semiconductor substrate, 14 denotes an n+ type region serving as a photodiode (photoelectric conversion region), 13 denotes a p+ type semiconductor region serving as a device separation region that separates the photoelectric conversion region 14 from an adjacent portion, 15 denotes an n+ type semiconductor region serving as a drain of a control MOSFET, 21 denotes the control MOSFET, 22 denotes a MOSFET of a source follower amplifier, 23 denotes a MOSFET of a horizontal selection switch, 24 denotes a load MOSFET of the source follower amplifier, 25 denotes a dark output transfer MOSFET, 26 denotes a light output transfer MOSFET, 27 denotes a dark output accumulation capacitance, and 28 denotes a light output accumulation capacitance.
In the p-type semiconductor substrate 11, as shown in FIG. 14, the photoelectric conversion region 14 is connected to a gate of the MOSFET 22 constituting the source follower amplifier via a wiring layer (not shown), and to the source or drain of the MOSFET 22 is connected a source or drain of the MOSFET 23 serving as the horizontal selection switch. Then, to the source or drain of the MOSFET 23 is connected a source or drain of the load MOSFET 24 forming the source follower amplifier. To the source or drain of both of the MOSFET 23 and MOSFET 24 are respectively connected a source or drain of the dark output transfer MOSFET 25 and the light output transfer MOSFET 26, and to the source or drain of the dark output transfer MOSFET 25 and the light output transfer MOSFET 26 are respectively connected the dark output accumulation capacitance 27 and the light output accumulation capacitance 28.
The CMOS sensor having such a construction operates as described below.
That is, at first, as shown in FIG. 14B, a control pulse ØR for the control MOSFET 21 is turned to a high level, and the n+ type semiconductor region 15 is set to a power supply voltage VDD, to reset the signal charge of the photoelectric conversion region 14. Then, as shown in FIG. 14C, the control pulse ØR for the control MOSFET 21 is made a low level voltage for preventing blooming.
During the signal charge accumulation, when due to the incident light, electron-hole pairs are generated in the region under the photoelectric conversion region 14, electrons accumulate in the depletion layer under the photoelectric conversion region 14, and holes are discharged through the p-type well layer 12. Here, in FIG. 14C, the region shown by grid-like hatching, having a potential deeper than the power supply voltage VDD shows that the region is not depleted. Since there is formed a potential barrier B by means of the control MOSFET 21, between the depletion layer formed in the p-type well layer 12 under the photoelectric conversion region 14, and the n+ type semiconductor region 15 serving as a floating diffusion layer, electrons exist under the photoelectric conversion region 14 during the photoelectric charge accumulation, as shown in FIG. 14C.
Subsequently, the potential of the photoelectric conversion region 14 changes depending on the number of accumulated electrons, and by outputting the potential change to the horizontal selection switch MOSFET 23 via the source of the source follower amplifier MOSFET 22 in the source follower operation, a photoelectric conversion characteristic having excellent linearity can be obtained.
Here, in the n+ type semiconductor region 15 serving as the floating diffusion layer, kTC noise due to reset is generated. However this can be removed by sampling and accumulating the dark-time output before the transfer of the signal electrons, and taking the difference with respect to the light-time output.
Recently, it has been proposed to unite various hardware such as a CPU, a memory, a standard/dedicated macro, an analog circuit and an image sensor portion (H/W integration), and various software such as image compression extensions, speech processing and communication functions (S/W integration) on one chip, and design a device as a xe2x80x9cSystem on Chipxe2x80x9d (SOC) in which an LSI unit is a semiconductor including a desired system/device functional operation. To produce a solid state imaging device as this SOC, it is required to produce the logic circuit portion 106 by utilizing heretofore accumulated technology and adapt to the solid state imaging device consolidating technology for integrating different processes on one chip.
Here, in the CMOS sensor obtained as an SOC, there has been a demand that the image sensor portion 101 is formed at the same time as the logic circuit portion 106 to thereby obtain the SOC, utilizing the CMOS process with the standard parameters widely used for processors, semiconductor memories such as DRAMs or the like and logic circuits, and these are formed on one chip in one process flow, thereby making it possible to share the production line with semiconductor memories and processors.
However, in the conventional solid state imaging device described above having compatibility with the CMOS manufacturing process, the impurity concentration in the p-type well layer 12 is set high for miniaturization of the MOS structure. Therefore the coupling capacitance between the p-type well layer 12 and the n+ type semiconductor region 14 increases so that the charge detection capacitance (particularly, the coupling capacitance related to the n+ type semiconductor region 14) increases. Hence there is a problem in that the detection sensitivity decreases. That is since the depletion layer at the connection portion between the p-type well layer 12 and the n+ type semiconductor region 14 is narrow, the photoelectric conversion rate due to the incident light (particularly, light on the red side having low energy and a long wavelength) decreases, causing a problem in that the detection sensitivity decreases.
To solve the problem of the decrease in detection sensitivity, it can be considered to simply reduce the concentration of the p-type well layer 12, and extend the depletion layer toward the p-type semiconductor substrate 11 side. However in such a case, there is a problem in that the threshold voltage and saturation current value of the transistor fluctuate. Moreover, the depletion layer extends not only toward the p-type semiconductor substrate 11 side, but also in the outward direction of the n+ type semiconductor region 14, seen in plan view, in particular, toward the n+ type semiconductor region 15. Hence, a so-called punch-through of the n+ type semiconductor region 14 and the n+ type semiconductor region 15 occurs, causing a problem in that the transistor characteristics (operating characteristics) decrease.
There is also a demand for improving the degree of integration and increasing the number of pixels per unit area. However, if the number of pixels per unit area is increased, respective basic cells are brought close to each other. In such a case, it is necessary to maintain a predetermined gap between these basic cells, in order to maintain separation characteristics between respective basic cells. However as described above, in the case where the concentration of the p-type well layer 12 is reduced to extend the depletion layer toward the p-type semiconductor substrate 11 side, there is a problem in that the depletion layer extends not only toward the p-type semiconductor substrate 11 side, but also toward the p+ type semiconductor region 13 side constituting the device separation region, causing a decrease in the device separation characteristics.
Moreover, as described above, when the concentration of the p-type well layer 12 is reduced, it is necessary to change established production parameters in the manufacturing method. Hence the p-type well layer 12 cannot be produced in the same step as the CMOS circuit manufacturing process having prescribed values for parameters, thus requiring an additional step. Therefore it is not possible to utilize the characteristics of the CMOS sensor where the logic circuit, analog circuit and A/D conversion circuit, etc. can be formed at the same time, and the image sensor portion 101 can be formed on the semiconductor chip the same for a semiconductor memory and a processor, and the production line can be shared with semiconductor memories and processors. Hence, a special process is used as with the CCD sensor, so that there is a possibility that the feature of the CMOS sensor where production costs are reduced, cannot be realized.
In view of the above situation, the present invention is aimed at achieving the following objects:
(a) To maintain transistor characteristics (operating characteristics);
(b) To improve detection sensitivity;
(c) To improve power conversion efficiency;
(d) To improve photoelectric conversion efficiency;
(e) To enable extension of the depletion layer;
(f) To reduce coupling capacitance;
(g) To maintain separation characteristics between pixels;
(h) To reduce the occurrence of crosstalk;
(i) To maintain high withstanding voltage characteristics;
(j) To make an SOC possible;
(k) To reduce process-wise load without changing standard parameters;
(l) To use standard macros and reduce production costs;
(m) To provide a solid state imaging device having the above described characteristics;
(n) To provide a manufacturing method for a solid state imaging devices having the above described characteristics;
Moreover, the present invention is aimed at achieving the following objects:
(o) To provide a photoelectric conversion device having the above described characteristics and a manufacturing method therefor;
(p) To provide a light receiving element having the above described characteristics and a manufacturing method therefor; and
(q) To provide a photocoupler having the above described characteristics and a manufacturing method therefor.
The photoelectric conversion device of the present invention solves the above described problems by having a first conductive type well layer provided on a semiconductor substrate and a second conductive type light receiving region (photoelectric conversion region) provided on the well layer, and at a position under the second conductive type light receiving region, there is provided a first conductive type impurity layer (depletion layer forming layer) in which an impurity concentration thereof is set to be lower than that of the well layer for enabling a reduction in coupling capacitance, such that at least a part of the first conductive type impurity layer is located inside of the second conductive type light receiving region, seen in plan view, for enabling extension of a depletion layer.
The present invention can be applied to a solid state imaging device which is an active XY addressing type CMOS sensor where a photoelectric conversion portion and a logic circuit portion (CMOS circuit portion) are formed on a semiconductor substrate with the same process, and a potential change due to charges generated in the photoelectric conversion portion is output.
The present invention can be applied to a light receiving element having a light receiving portion having a light receiving region, and a logic circuit portion used for control or signal processing in the light receiving portion.
The present invention can be applied to a photocoupler comprising the above described light receiving element and a corresponding light emission element.
With the present invention, the first conductive type impurity layer (depletion layer forming layer) can have a layer thickness approximately the same as that of the well layer located at a position under the second conductive type light receiving region.
Here, the first conductive type impurity layer (depletion layer forming layer) may be connected to the semiconductor substrate being of a first conductive type, or an impurity concentration of the first conductive type impurity layer (depletion layer forming layer) may be set to be the same as that of the semiconductor substrate being of the first conductive type. Moreover the first conductive type impurity layer (depletion layer forming layer) may be integrated with the semiconductor substrate being of the first conductive type.
In the present invention, a first conductive type deep well layer is provided in the semiconductor substrate, in contact with a lower side of the first conductive type well layer, and an impurity concentration thereof is set to be the same as or lower than that of the well layer. An impurity concentration of the first conductive type deep well layer can be set to be higher than that of the semiconductor substrate being of the first conductive type, or higher than that of the first conductive type impurity layer (depletion layer forming layer) in contact with the first conductive type deep well layer.
The present invention solves the above described problems by having a first conductive type well layer provided on a semiconductor substrate and a second conductive type light receiving region (photoelectric conversion region) provided on the well layer, and at a position under the second conductive type light receiving region, there is provided a second conductive type impurity layer (reverse depletion layer forming layer) in which an impurity concentration thereof is set to be lower than that of the light receiving region for enabling a reduction in coupling capacitance, such that at least a part of the second conductive type impurity layer is located inside of the second conductive type light receiving region, seen in plan view, for enabling extension of a depletion layer.
The present invention may have a construction such that a second conductive type impurity layer (reverse depletion layer forming layer) is provided in contact with a lower side of the second conductive type light receiving region, such that an impurity concentration thereof is set to be lower than that of the second conductive type light receiving region (photoelectric conversion region), and at least a part of the second conductive type impurity layer is located inside of the second conductive type light receiving region (photoelectric conversion region), seen in plan view, and the second conductive type impurity layer (reverse depletion layer forming layer) is located between the first conductive type impurity layer (depletion layer forming layer) and the second conductive type light receiving region, and the first conductive type impurity layer (depletion layer forming layer) is provided such that at least a part thereof is located inside of the second conductive type impurity layer (reverse depletion layer forming layer), seen in plan view, and the total thickness of the second conductive type impurity layer (reverse depletion layer forming layer) and the first conductive type impurity layer (depletion layer forming layer) has approximately the same layer thickness as that of the well layer located at a position under the second conductive type light receiving region.
With the present invention, the first conductive type impurity layer (depletion layer forming layer) in contact with the second conductive type light receiving region may comprise a plurality of layers. Moreover this may have a sloping impurity concentration, and the impurity concentration of the respective layers or the sloping impurity concentration may be set so as to decrease from the deep side of the semiconductor substrate toward the second conductive type light receiving region. Furthermore, the first conductive type impurity layer (depletion layer forming layer) in contact with the second conductive type impurity layer (reverse depletion layer forming layer) may comprise a plurality of layers or have a sloping impurity concentration, and the impurity concentration of the respective layers or the sloping impurity concentration may be set so as to decrease from the deep side of the semiconductor substrate toward the second conductive type impurity layer (reverse depletion layer forming layer). Furthermore, the second conductive type impurity layer (reverse depletion layer forming layer) in contact with the second conductive type light receiving region may comprise a plurality of layers or have a sloping impurity concentration, and the impurity concentration of the respective layers or the sloping impurity concentration may be set so as to decrease from the second conductive type light receiving region side toward a deep side of the semiconductor substrate.
In the present invention, it is possible to select a technique whether the semiconductor substrate is the first conductive type or the second conductive type.
In the present invention, it is possible to set the impurity concentration of the second conductive type light receiving region to be lower than the impurity concentration of an other second conductive type diffusion layer.
In the present invention, it is possible to have a logic circuit portion which is driven by the voltage by means of an output from the second conductive type light receiving region.
In the present invention, preferably various hardware such as a CPU, a memory, a standard/dedicated macro, an analog circuit and an image sensor portion (H/W integration) and various software such as image compression extensions, speech processing and communication functions (S/W integration) are composed on one chip, so that an LSI unit is produced as SOC xe2x80x9cSystem on Chipxe2x80x9d which is a semiconductor including a desired system/device functional operation.
The present invention is a manufacturing method for a photoelectric conversion device having a first conductive type well layer provided on a semiconductor substrate and a second conductive type light receiving region (photoelectric conversion region) provided on the well layer, and at a position under the second conductive type light receiving region, there is provided a first conductive type impurity layer (depletion layer forming layer) in which the impurity concentration thereof is set to be lower than that of the well layer for enabling a reduction in coupling capacitance, such that at least a part of the first conductive type impurity layer is located inside of the second conductive type light receiving region, seen in plan view, for enabling extension of a depletion layer. The above described problems are solved by having a step for forming a first conductive type well layer on the semiconductor substrate; a step for forming the second conductive type light receiving region (photoelectric conversion region) on the well layer; and a step for forming the first conductive type impurity layer (depletion layer forming layer).
The present invention is a manufacturing method for a photoelectric conversion device having a first conductive type well layer provided on a semiconductor substrate, and a second conductive type light receiving region (photoelectric conversion region) provided on the well layer, and at a position under the second conductive type light receiving region, there is provided a second conductive type impurity layer (reverse depletion layer forming layer) in which an impurity concentration thereof is set to be lower than that of the light receiving region for enabling a reduction in coupling capacitance, such that at least a part of the second conductive type impurity layer is located inside of the second conductive type light receiving region, seen in plan view, for enabling extension of a depletion layer. The above described problems are solved by having a step for forming the first conductive type well layer on the semiconductor substrate; a step for forming the second conductive type light receiving region (photoelectric conversion region) on the well layer; and a step for forming the second conductive type impurity layer (reverse depletion layer forming layer).
The present invention may have a step for forming a first conductive type deep well layer wherein an impurity concentration thereof is set to be higher than that of the semiconductor substrate being of the first conductive type, or an impurity concentration thereof is set to be lower than that of the well layer, or an impurity concentration thereof is set to be higher than that of the first conductive type impurity layer (depletion layer forming layer).
The present invention may have a step for forming a second conductive type impurity layer (reverse depletion layer forming layer) provided in contact with a lower side of the second conductive type light receiving region such that an impurity concentration thereof is set to be lower than that of the second conductive type light receiving region (photoelectric conversion region), and at least a part of the second conductive type impurity layer is located inside of the second conductive type light receiving region (photoelectric conversion region), seen in plan view. Moreover, the present invention may have a step for forming a second conductive type impurity layer (reverse depletion layer forming layer) between the first conductive type impurity layer (depletion layer forming layer) and the second conductive type light receiving region, such that an impurity concentration thereof is set to be lower than that of the light receiving region, and at least a part thereof is located inside of the light receiving region, seen in plan view, and at least a part thereof is located outside of the first conductive type impurity layer (depletion layer forming layer), seen in plan view.
The present invention may have a step for forming the second conductive type light receiving region having an impurity concentration set to be lower than that of an other second conductive type diffusion layer.
In the present invention, preferably various hardware such as a CPU, a memory, a standard/dedicated macro, an analog circuit and an image sensor portion (H/W integration) and various software such as image compression extensions, speech processing and communication functions (S/W integration) are composed on one chip, so that an LSI unit is produced as an SOC xe2x80x9cSystem on Chipxe2x80x9d which is a semiconductor including a desired system/device functional operation.
In the photoelectric conversion device of the present invention, a first conductive type impurity layer (depletion layer forming layer) having an impurity concentration set to be lower than the well layer, is provided at a position under the second conductive type light receiving region, for enabling a reduction in the coupling capacitance. As a result, the coupling capacitance in a connection portion between the second conductive type light receiving region (photoelectric conversion region) and the first conductive type impurity layer (depletion layer forming layer) is reduced to improve the power conversion efficiency. Moreover, by providing the first conductive type impurity layer (depletion layer forming layer) such that at least a part thereof is located inside of the second conductive type light receiving region, seen in plan view, for enabling extension of the depletion layer, then when the depletion layer is extended toward the semiconductor substrate side, extension of the depletion layer in the outward direction of the second conductive type light receiving region, seen in plan view, can be prevented. Therefore, parasitic capacitance can be reduced, enabling an increase of the potential change due to the signal charge, and an improvement in the power conversion efficiency. As a result, the photoelectric conversion efficiency can be improved.
Furthermore, by providing the first conductive type impurity layer (depletion layer forming layer) located inside of the second conductive type light receiving region, seen in plan view, then when the depletion layer is extended toward the semiconductor substrate deep side, extension of the depletion layer in the outward direction of the second conductive type light receiving region, seen in plan view, can be prevented. Hence, it becomes possible to improve the photoelectric conversion efficiency, while maintaining the transistor characteristics (operating characteristics) and the device separation characteristics.
By applying the present invention to a solid state imaging device which is an active XY addressing type CMOS sensor wherein a photoelectric conversion region and a logic circuit portion (CMOS circuit portion) are formed on a semiconductor substrate with the same process, and a potential change due to charges generated in the photoelectric conversion region is output, a CPU, a memory, a standard/dedicated macro, an analog circuit and an image sensor portion can be formed at the same time with the CMOS process, by means of the standard parameters widely used for processors, semiconductor memories such as DRAMs, and logic circuits, enabling a reduction in the manufacturing steps and a reduction in process-wise load, compared to the CCD sensor which uses a special process to which it is difficult to directly apply the CMOS circuit manufacturing process.
By applying the present invention to a light receiving element having a light receiving portion and a logic circuit portion used for control or signal processing in the light receiving portion (photeoelectric conversion portion), wherein the photeoelectric conversion portion and the logic circuit portion (CMOS circuit portion or the like) are formed on a semiconductor substrate with the same process, the operating characteristics of the light receiving element can be improved. Moreover the manufacturing steps are reduced compared to a light receiving element produced using a special manufacturing process, enabling a reduction in process-wise load.
By applying the present invention to a photocoupler comprising the above described light receiving element and a corresponding light emission element, the operating characteristics of the light receiving element can be improved. Moreover the manufacturing steps are reduced as described above, enabling a reduction in process-wise load.
With the present invention, the first conductive type impurity layer (depletion layer forming layer) has a layer thickness approximately the same as that of the well layer located at a position under the second conductive type light receiving region. Hence the coupling capacitance is reduced in a connection portion between the second conductive type light receiving region and the first conductive type impurity layer (depletion layer forming layer), to improve the power conversion efficiency, as well as enabling extension of the depletion layer toward the deep side of the semiconductor substrate. In addition, while maintaining the transistor characteristics (operating characteristics), the parasitic capacitance can be reduced, enabling an increase in the potential change due to the signal charge, and an improvement in the power conversion efficiency. Moreover, the photoelectric conversion efficiency can be improved. This result enables an improvement in detection sensitivity.
Here, the first conductive type impurity layer (depletion layer forming layer) is connected to the semiconductor substrate being of the first conductive type, or an impurity concentration of the first conductive type impurity layer (depletion layer forming layer) is set to be the same as that of the semiconductor substrate being of the first conductive type. Furthermore, since the first conductive type impurity layer (depletion layer forming layer) is integrated with the semiconductor substrate being of the first conductive type, it is possible to reduce the manufacturing steps, to thereby reduce process-wise load and reduce production costs.
In the present invention, the first conductive type deep well layer is provided on the semiconductor substrate, with an impurity concentration set to be the same as or lower than that of the well layer, and the impurity concentration of the first conductive type deep well layer is set to be higher than that of the semiconductor substrate being of the first conductive type, or higher than that of the first conductive type impurity layer (depletion layer forming layer) in contact with the first conductive type deep well layer. As a result, the coupling capacitance is reduced at the connection portion between the first conductive type deep well layer and the first conductive type impurity layer (depletion layer forming layer), enabling improvement in the power conversion efficiency. That is, crosstalk where floating charges generated in the deep portion of the semiconductor substrate leak into adjacent other pixels can be prevented by the first conductive type deep well layer provided therein.
The present invention has a first conductive type well layer provided on a semiconductor substrate and a second conductive type light receiving region (photoelectric conversion region) provided on the well layer, and at a position under the second conductive type light receiving region, there is provided a second conductive type impurity layer (reverse depletion layer forming layer) in which an impurity concentration thereof is set to be lower than that of the light receiving region for enabling a reduction in the coupling capacitance, such that at least a part of the second conductive type impurity layer is located inside of the second conductive type light receiving region, seen in plan view, for enabling extension of a depletion layer. As a result, extension of the depletion layer toward the semiconductor substrate deep side, at the connection portion of the second conductive type light receiving region and the second conductive type impurity layer (reverse depletion layer forming layer) is possible, enabling a reduction in the coupling capacitance and an improvement in photoelectric conversion efficiency.
Furthermore, by providing the second conductive type impurity layer (reverse depletion layer forming layer) located inside of the second conductive type light receiving region (photoelectric conversion region), seen in plan view, then when the depletion layer is extended toward the semiconductor substrate deep side, extension of the depletion layer in the outward direction of the second conductive type light receiving region, seen in plan view, can be prevented. Hence, the photoelectric conversion efficiency can be improved, while maintaining the transistor characteristics (operating characteristics) and the device separation characteristics.
In the present invention, the second conductive type impurity layer (reverse depletion layer forming layer) is located between the first conductive type impurity layer (depletion layer forming layer) and the second conductive type light receiving region, and the total thickness of the second conductive type impurity layer (reverse depletion layer forming layer) and the first conductive type impurity layer (depletion layer forming layer) has approximately the same layer thickness as that of the well layer located at a position under the second conductive type light receiving region. As a result, the coupling capacitance is reduced at the connection portion between the second conductive type impurity layer (reverse depletion layer forming layer) and the first conductive type impurity layer (depletion layer forming layer), enabling improvement in the power conversion efficiency. Moreover, since the second conductive type impurity layer (reverse depletion layer forming layer) is provided such that at least a part of the second conductive type impurity layer is located inside of the second conductive type light receiving region, seen in plan view, and the first conductive type impurity layer (depletion layer forming layer) is provided such that at least a part of the first conductive type impurity layer is located inside of the second conductive type impurity layer (reverse depletion layer forming layer), seen in plan view, the coupling capacitance can be reduced in each connection portion. In addition, when the depletion layer is extended toward the deep side of the semiconductor substrate, extension of the depletion layer in the outward direction of the second conductive type light receiving region, seen in plan view, can be prevented. Moreover, while the transistor characteristics (operating characteristics) and the separation characteristics between pixels are maintained, the photoelectric conversion efficiency can be improved.
In the present invention, the first conductive type impurity layer (depletion layer forming layer) in contact with the second conductive type light receiving region comprises a plurality of layers, or has a sloping impurity concentration, and the impurity concentration or the sloping impurity concentration of respective layers is set so as to decrease from the semiconductor substrate side toward the second conductive type light receiving region. Hence, the coupling capacitance can be reduced at this connection portion and at other connection portions with the semiconductor substrate or with the first conductive type deep well layer, enabling improvement in the power conversion efficiency. That is, crosstalk where floating charges generated in the deep portion of the semiconductor substrate leak into adjacent other pixels can be prevented by the first conductive type deep well layer provided therein.
Moreover, the first conductive type impurity layer (depletion layer forming layer) in contact with the second conductive type impurity layer (reverse depletion layer forming layer) comprises a plurality of layers or has a sloping impurity concentration, and it is set such that the impurity concentration or the sloping impurity concentration of respective layers decreases from the semiconductor substrate side toward the second conductive type impurity layer (reverse depletion layer forming layer). As a result, the coupling capacitance can be reduced at the connection portion between these and at other connection portions with the semiconductor substrate or with the first conductive type deep well layer, enabling improvement in the power conversion efficiency.
Furthermore, the second conductive type impurity layer (reverse depletion layer forming layer) in contact with the second conductive type light receiving region comprises a plurality of layers, or has a sloping impurity concentration, and the impurity concentration or the sloping impurity concentration of respective layers is set so as to decrease from the second conductive type light receiving region side toward the semiconductor substrate side. Hence, the coupling capacitance can be reduced at this connection portion and at other connection portions with the first conductive type impurity layer (depletion layer forming layer), enabling improvement in the power conversion efficiency. As a result, maintenance of high withstanding voltage characteristics, and a further improvement in photoelectric conversion efficiency can be achieved.
In the present invention, it is possible to select a technique where the semiconductor substrate is of a first conductive type or of a second conductive type together with the existence of a first conductive type deep well layer. When the semiconductor substrate is of the second conductive type, charges photoelectrically converted in the deep portion of the second conductive type semiconductor substrate can be prevented from flowing into adjacent pixels, thereby reducing the occurrence of crosstalk.
In the present invention, the impurity concentration of the second conductive type light receiving region (photoelectric conversion region) is set to be lower than that of an other second conductive type diffusion layer, thereby enabling a reduction in parasitic capacitance.
At the same time, by setting the impurity concentration of the second conductive type light receiving region to be lower than that of an other second conductive type diffusion layer serving as a reset drain region which is, for example, a drain of the control gate, the second conductive type light receiving region (photoelectric conversion region) which is converted into floating diffusion differs from the other second conductive type diffusion layer. Hence a reduction is possible in image defects generally referred to as xe2x80x9cwhite defectsxe2x80x9d due to leaks resulting from defects occurring at the time of forming the second conductive type light receiving region (photoelectric conversion region). Therefore the operating characteristics can be improved.
When the present invention has a logic circuit portion which is driven by the voltage by means of the output from the second conductive type light receiving region (photoelectric conversion region), the power conversion efficiency can be improved as described above, and operating characteristics can be improved.
The present embodiment composes various hardware such as a CPU, a memory, a standard/dedicated macro, an analog circuit and an image sensor portion (H/W integration), and various software such as image compression extensions, speech processing and communication functions (S/W integration) on one chip, and this is produced as an SOC (System on Chip) in which an LSI unit is a semiconductor including a desired system/device functional operation. Hence, compared to the CCD sensor which uses a special process to which it is difficult to directly apply the CMOS circuit manufacturing process, a CPU, a memory, a standard/dedicated macro, an analog circuit, and an image sensor portion etc., can be formed at the same time, by the CMOS process by means of the standard parameters widely used for processors, semiconductor memories such as DRAMs, and logic circuits, enabling a reduction in the manufacturing steps, a reduction in process-wise load, and a reduction in production costs.
The present invention is a manufacturing method for a photoelectric conversion device having a first conductive type well layer provided on a semiconductor substrate and a second conductive type light receiving region (photoelectric conversion region) provided on the well layer, and at a position under the second conductive type light receiving region, there is provided a first conductive type impurity layer (depletion layer forming layer) in which the impurity concentration thereof is set to be lower than that of the well layer for enabling a reduction in the coupling capacitance, such that at least a part of the first conductive type impurity layer is located inside of the second conductive type light receiving region, seen in plan view, for enabling extension of the depletion layer, wherein the manufacturing method adopts means having: a step for forming the first conductive type well layer on the semiconductor substrate; a step for forming the second conductive type light receiving region (photoelectric conversion region) on the well layer; and a step for forming the first conductive type impurity layer (depletion layer forming layer). Alternatively, the present invention is a manufacturing method for a photoelectric conversion device having a first conductive type well layer provided on a semiconductor substrate and a second conductive type light receiving region (photoelectric conversion region) provided on the well layer, and at a position under the second conductive type light receiving region, there is provided a second conductive type impurity layer (reverse depletion layer forming layer) in which the impurity concentration thereof is set to be lower than that of the second conductive type light receiving region for enabling a reduction in the coupling capacitance, such that at least a part of the second conductive type impurity layer is located inside of the second conductive type light receiving region, seen in plan view, for enabling extension of the depletion layer, wherein the manufacturing method adopts means having: a step for forming the first conductive type well layer on the semiconductor substrate; a step for forming the second conductive type light receiving region (photoelectric conversion region) on the well layer; and a step for forming the second conductive type impurity layer (reverse depletion layer forming layer). As a result, the coupling capacitance can be reduced, the depletion layer can be extended, the high withstanding voltage characteristics, the transistor characteristics (operating characteristics) and the separation characteristics between pixels can be maintained, the power conversion efficiency as well as the photoelectric conversion efficiency can be improved, and the detection sensitivity can be improved. In addition, compared to the CCD sensor which uses a special process to which it is difficult to directly apply the CMOS circuit manufacturing process, a CPU, a memory, a standard/dedicated macro, an analog circuit and an image sensor portion can be formed at the same time with the CMOS process, by means of the standard parameters widely used for processors, semiconductor memories such as DRAMs, and logic circuits, enabling a reduction in the manufacturing steps and a reduction in process-wise load.
The present invention can provide a manufacturing method for a photoelectric conversion device, wherein by having a step for forming the first conductive type deep well layer in which the impurity concentration thereof is set to be higher than that of the semiconductor substrate being of the first conductive type, or lower than that of the well layer, or higher than that of the first conductive type impurity layer (depletion layer forming layer), it becomes possible to select the semiconductor substrate being of the first conductive type or the second conductive type. Moreover prevention of the occurrence of crosstalk, a further reduction in coupling capacitance, and maintenance of the high withstanding voltage characteristics can be effected.
The present invention can provide a manufacturing method for a photoelectric conversion device, wherein by having a step for forming the second conductive type impurity layer (reverse depletion layer forming layer) between the first conductive type impurity layer (depletion layer forming layer) and the second conductive type light receiving region, such that the impurity concentration thereof is set to be lower than that of the second conductive type light receiving region, and at least a part thereof is located inside of the second conductive type light receiving region, seen in plan view, and at least a part thereof is located outside of the first conductive type impurity layer (depletion layer forming layer), seen in plan view, extension of the depletion layer is made possible, the coupling capacitance can be reduced, and the operating characteristics and the separation characteristics between pixels are maintained.
The present invention can provide a manufacturing method for a photoelectric conversion device, which can further reduce parasitic capacitance, by having a step for forming the second conductive type light receiving region with an impurity concentration set to be lower than that of an other second conductive type diffusion layer.
At the same time, by setting the impurity concentration of the second conductive type light receiving region to be lower than that of an other second conductive type diffusion layer serving as a reset drain region which is, for example, a drain of the control gate, the second conductive type light receiving region (photoelectric conversion region) which becomes floating diffusion differs from the other second conductive type diffusion layer. Hence a reduction is possible in image defects generally referred to as xe2x80x9cwhite defectxe2x80x9d due to leaks resulting from defects occurring at the time of forming the second conductive type light receiving region (photoelectric conversion region). Hence, the operating characteristics can be improved.
The present embodiment composes various hardware such as a CPU, a memory, a standard/dedicated macro, an analog circuit and an image sensor portion (H/W integration), and various software such as image compression extensions, speech processing and communication functions (S/W integration) on one chip, and this is produced as an SOC (System on Chip) in which an LSI unit is a semiconductor including a desired system/device functional operation. Hence, compared to the CCD sensor which uses a special process to which it is difficult to directly apply the CMOS circuit manufacturing process, a CPU, a memory, a standard/dedicated macro, an analog circuit, and an image sensor portion etc., can be formed at the same time, by the CMOS process by means of the standard parameters widely used for processors, semiconductor memories such as DRAMs, and logic circuits, enabling a reduction in the manufacturing steps, a reduction in process-wise load, and a reduction in production costs.